张芳, 赵东旭, 肖志涛, 等. 单幅图像超分辨率重建技术研究进展[J]. 自动化学报, 2022, 48(11): 2634-2654.
AGUSTSSON E, TIMOFTE R, VAN GOOL L. Anchored Regression Networks Applied to Age Estimation and Super Resolution[C]//2017 IEEE International Conference on Computer Vision (ICCV). Venice, Italy. IEEE, 2017: 1652-1661.
CHEN M J, HUANG C H, LEE W L. A Fast Edge-Oriented Algorithm for Image Interpolation[J]. Image and Vision Computing, 2005, 23(9): 791-798. doi: 10.1016/j.imavis.2005.05.005
CHOI J S, KIM M. Super-Interpolation with Edge-Orientation-Based Mapping Kernels for Low Complex 2×Upscaling[J]. IEEE Transactions on Image Processing, 2016, 25(1): 469-483. doi: 10.1109/TIP.2015.2507402
DONG C, LOY C C, HE K M, et al. Learning a Deep Convolutional Network for Image Super-Resolution[C]//European Conference on Computer Vision. Cham: Springer, 2014: 184-199.
TIMOFTE R, DE SMET V, VAN GOOL L. A+: Adjusted Anchored Neighborhood Regression for Fast Super-Resolution[C]//Asian Conference on Computer Vision. Cham: Springer, 2015: 111-126.
LI X, ORCHARD M T. New Edge Directed Interpolation[C]//Proceedings 2000 International Conference on Image Processing (Cat. No. 00CH37101). Vancouver, BC, Canada. IEEE, 2002: 311-314.
YANG C Y, YANG M H. Fast Direct Super-Resolution by Simple Functions[C]//2013 IEEE International Conference on Computer Vision. Sydney, NSW, Australia. IEEE, 2013: 561-568.
CHANG J W, KANG K W, KANG S J. An Energy-Efficient FPGA-Based Deconvolutional Neural Networks Accelerator for Single Image Super-Resolution[J]. IEEE Transactions on Circuits and Systems for Video Technology, 2020, 30(1): 281-295. doi: 10.1109/TCSVT.2018.2888898
KIM Y, CHOI J S, KIM M. 2X Super-Resolution Hardware Using Edge-Orientation-Based Linear Mapping for Real-Time 4K UHD 60 Fps Video Applications[J]. IEEE Transactions on Circuits and Systems Ⅱ: Express Briefs, 2018, 65(9): 1274-1278. doi: 10.1109/TCSII.2018.2799577
LEE J, PARK I C. High-Performance Low-Area Video Up-Scaling Architecture for 4-K UHD Video[J]. IEEE Transactions on Circuits and Systems Ⅱ: Express Briefs, 2017, 64(4): 437-441. doi: 10.1109/TCSII.2016.2563818
SHIAU Y H, HUANG K Y, CHEN P Y, et al. A Low-Cost Hardware Design of Learning-Based One-Dimensional Interpolation for Real-Time Video Applications at the Edge[J]. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2021, 11(4): 677-689. doi: 10.1109/JETCAS.2021.3121070
SIVA M V, JAYAKUMAR E P. A Low Cost High Performance VLSI Architecture for Image Scaling in Multimedia Applications[C]//2020 7th International Conference on Signal Processing and Integrated Networks (SPIN). Noida, India. IEEE, 2020: 278-283.
NUNO-MAGANDA M A, ARIAS-ESTRADA M O. Real-time FPGA-based Architecture for Bicubic Interpolation: An Application for Digital Image Scaling[C]//2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05). Puebla, Mexico. IEEE, 2005: 8-11.
ZHANG Y S, LI Y H, ZHEN J, et al. The Hardware Realization of the Bicubic Interpolation Enlargement Algorithm Based on FPGA[C]//2010 Third International Symposium on Information Processing. Qingdao, Shandong, China. IEEE, 2020: 277-281.
KEYS R. Cubic Convolution Interpolation for Digital Image Processing[J]. IEEE Transactions on Acoustics, Speech, and Signal Processing, 1981, 29(6): 1153-1160. doi: 10.1109/TASSP.1981.1163711
GIRSHICK R, DONAHUE J, DARRELL T, et al. Rich Feature Hierarchies for Accurate Object Detection and Semantic Segmentation[EB/OL]. (2014-10-22)[2024-02-22]. https://arxiv.org/pdf/1311.2524.pdf.
KRIZHEVSKY A, SUTSKEVER I, HINTON G E. Image Net Classification with Deep Convolutional Neural Networks[J]. Communications of the ACM, 2017, 60(6): 84-90. doi: 10.1145/3065386
SIMONYAN K, ZISSERMAN A. Very Deep Convolutional Networks for Large-Scale Image Recognition[EB/OL]. (2015-04-10)[2024-02-22]. https://arxiv.org/pdf/1409.1556v6.pdf.
ZEILER M D, KRISHNAN D, TAYLOR G W, et al. Deconvolutional Networks[C]//2010 IEEE Computer Society Conference on Computer Vision and Pattern Recognition. San Francisco, CA, USA. IEEE, 2010: 2528-2535.
ZHANG X Y, DAS S, NEOPANE O, et al. A Design Methodology for Efficient Implementation of Deconvolutional Neural Networks on an FPGA[EB/OL]. (2017-05-07)[2022-10-09]. https://arxiv.org/abs/1705.02583v1.